Conventional oscillators and, in particular, digital-controlled oscillators (DCOs) are limited in their ability to introduce a phase adjustment smaller than the period of the reference clock in the oscillator. Thus, the reference clock period provides a quantization limit on the time precision of a phase-locked loop (PLL) that incorporates the DCO. Typically, to achieve greater precision would require increasing the frequency of the reference clock in the oscillator, although this approach has many associated problems. In such an approach, a higher frequency clock may be supplied or, alternatively, circuitry may be introduced to increase the clock frequency. However, such an increase in the frequency of the reference clock may increase the cost and complexity of the supporting or other circuitry and increase the power consumption of the oscillator. Likewise, increasing the frequency may, in some circumstances, not be a viable option for technological reasons. Thus, a need exists for an oscillator having the capability to introduce a phase adjustment smaller than the period of the reference clock in the oscillator.